16 mutext lock/unlocks per query?

Rick Jones raj at cup.hp.com
Wed Dec 5 22:23:44 UTC 2001

> > I'm reasonably certain that the instruction does not have to flush
> > the caches.
> so am i, but the writes that are in the pipe headed out of the cpu
> into the memory subsystem might have to be stalled to make this
> instruction work.  iirc, on some cpu's the addresses of these writes
> are CAM-accessable from within the alu which means TSI won't stall the
> pipeline.

i'll ask around if it is important enough, otherwise, i'll go back to
trying to ge tthe 8way system (PA) setup.

Wisdom Teeth are impacted, people are affected by the effects of events.
these opinions are mine, all mine; HP might not want them anyway... :)
feel free to post, OR email to raj in cup.hp.com  but NOT BOTH...

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