16 mutext lock/unlocks per query?

[Rick Jones]

> > I'm reasonably certain that the instruction does not have to flush
> > the caches.
> 
> so am i, but the writes that are in the pipe headed out of the cpu
> into the memory subsystem might have to be stalled to make this
> instruction work.  iirc, on some cpu's the addresses of these writes
> are CAM-accessable from within the alu which means TSI won't stall the
> pipeline.

i'll ask around if it is important enough, otherwise, i'll go back to
trying to ge tthe 8way system (PA) setup.

rick
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