BIND 10 trac910, created. dfd8332b1a958ed9aeb6ae423ea937b5e08024f8 [trac910] documentation update

[BIND 10 source code commits]

The branch, trac910 has been created
        at  dfd8332b1a958ed9aeb6ae423ea937b5e08024f8 (commit)

- Log -----------------------------------------------------------------
commit dfd8332b1a958ed9aeb6ae423ea937b5e08024f8
Author: JINMEI Tatuya <jinmei at isc.org>
Date:   Thu Jul 14 00:16:57 2011 -0700

    [trac910] documentation update

commit 54c3708f45c72065cefd4d6013be5467bee65f85
Author: JINMEI Tatuya <jinmei at isc.org>
Date:   Thu Jul 14 00:01:48 2011 -0700

    [trac910] completed TSIG+TC support: added a minor case of too many questions.

commit 146c48357b32d26019675834eda1daddde95302c
Author: JINMEI Tatuya <jinmei at isc.org>
Date:   Wed Jul 13 23:36:41 2011 -0700

    [trac910] revised Question::toWire() so that it handles truncation case.
    This is not directly related to the subject of this ticket, but
    would be necessary to complete the TSIG + TC bit support.

commit 62f912bd96a5fefeb0eb8b017ff12335810483b0
Author: JINMEI Tatuya <jinmei at isc.org>
Date:   Wed Jul 13 14:12:36 2011 -0700

    [trac910] updated the python binding part and tests for the TSIG + TC bit cases.

commit 829edd5488aa90324ddc4036dbaf4f2578be9e76
Author: JINMEI Tatuya <jinmei at isc.org>
Date:   Sat Jul 9 00:24:27 2011 -0700

    [trac910] refactor the python test regarding TSIG: now we have
    fix_current_time(), we don't have to strip mutable TSIG fields.
    also generalized __common_tsigquery_setup() for later extensions.

commit d81a47d3366b6c6ed14edff69188b60ed3655f28
Author: JINMEI Tatuya <jinmei at isc.org>
Date:   Sat Jul 9 00:12:10 2011 -0700

    [trac910] supported various uncommon or very rare cases

commit a29b113e5b418921dffaf9b4cfc562ae887a7960
Author: JINMEI Tatuya <jinmei at isc.org>
Date:   Fri Jul 8 23:19:43 2011 -0700

    [trac910] handle a boundary condition that doesn't cause truncation.

commit 5024b68a04ecc7ff1c73299fa986cac740cb3e8b
Author: JINMEI Tatuya <jinmei at isc.org>
Date:   Fri Jul 8 18:35:20 2011 -0700

    [trac910] TSIG + TC support, 2nd part: add the case where TSIG itself
    triggers truncation.  added missing testdata files.

commit 56b188c6e4e36a28b54cab442677e2fa748f0bae
Author: JINMEI Tatuya <jinmei at isc.org>
Date:   Fri Jul 8 18:01:45 2011 -0700

    [trac910] refactored test code a bit to unify TSIG check tests

commit d7d60797272f02e6f3f09b659922c71f2c49ffec
Author: JINMEI Tatuya <jinmei at isc.org>
Date:   Fri Jul 8 17:41:54 2011 -0700

    [trac910] supported TSIG+TC case, first step: if TC is set even before
    adding the TSIG, clear everything.

commit 570bbcef51aa6a5bc920faabd850cd6a86c0d421
Author: JINMEI Tatuya <jinmei at isc.org>
Date:   Fri Jul 8 14:58:49 2011 -0700

    [trac910] added a new method getTSIGLength() to TSIGContext, which will be
    necessary for TC bit support.

commit e8e411dd27068279b58bc3527d1b60878ed19d0b
Author: JINMEI Tatuya <jinmei at isc.org>
Date:   Fri Jul 8 00:13:21 2011 -0700

    [trac910] pre-work refactoring: precreate an HMAC in the TSIGContextImpl
    constructor (if possible) so that the expected size of resulting TSIG RR
    can be calculated immediately before signing.

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